Wire Load Model: WLM

WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it. Prior to Routing stage, net parasitics and delays cannot be accurately determined. So, to predict delay we need to know the parasitics associated with interconnect/net:

1. Resistance
2. Capacitance
3. Area of the nets. 

 But at the pre-routing stage, we know only the fanout of net and the size of the block that the net belongs to. We can’t predict the resistance of the various pieces of the interconnect path, since we don’t know the shape of interconnect for a net. However, we can estimate the total length of the interconnect and thus estimate the total capacitance.

We estimate interconnect length by collecting statistics from previously routed chips and analyzing the results. From these statistics we create tables that predict the interconnect capacitance as a function of net fanout and block size. WLM can come from your library or from a floor planning tool. It is the method to initially estimate your delays and is usually overly pessimistic.

WLM analysis has three modes:

So, we can say, wireload model is basically a set of tables of
1. Net fanout vs Load
2. Net fanout vs Resistance
3. Net fanout vs Area And it is required for compile to estimate interconnect wiring delays .In this all attributes like area, resistance, capacitance, slope and fan-out are given per unit length.

How are net resistance and capacitance calculated with Wireload Models?

• Simple Table Lookup is performed

Some Important facts about WLM:

1. There are no standards for the wire load tables themselves, but there are some standards for their use and for presenting the extracted loads.
2. Wire load tables often present loads in terms of a standard load that is usually the input capacitance of a two input NAND gate with a 1X (default) drive strength.
3.  
4.  
5. The following are few snapshot of the different format of wire load model.
   wire_load("WLM1")      {                                    
     resistance  :         0.0006        ;------>R per unit length
     capacitance :       0.0001        ;------> C per unit length
     area :                   0.1             ;------> Area per unit length
     slope         :         1.5             ;------> Used for linear extrapolation
     fanout_length(1,  0.002)         ; ------> at fanout “1” length of the wire is 0.002
   fanout_length(2,  0.006);
   fanout_length(3,  0.009);
   fanout_length(4,  0.015);
   fanout_length(5,  0.020);
   fanout_length(7,  0.028);           ------> at fanout “7” length of the wire is 0.028
   fanout_length(8,  0.030);
   fanout_length(9,  0.035);
   fanout_length(10, 0.040);
   }
   wire_load("WLM2") {
            fanout_length(  1, 1 );
            fanout_length(  2, 2 );
             fanout_capacitance( 1, 0.002 );
             fanout_capacitance( 2, 0.004 );
             fanout_capacitance( 3, 0.006 );
             fanout_capacitance( 4, 0.008 );
             fanout_capacitance( 5, 0.010 );
             fanout_capacitance( 6, 0.013 );
             fanout_capacitance( 7, 0.015 );
             fanout_capacitance( 8, 0.019 );
             fanout_capacitance( 9, 0.023 );
             fanout_capacitance( 10, 0.027);
            
             fanout_resistance( 1, 0.01 );
             fanout_resistance( 2, 0.015 );
             fanout_resistance( 3, 0.022 );
             fanout_resistance( 4, 0.026 );
             fanout_resistance( 5, 0.030 );
             fanout_resistance( 6, 0.035 );
             fanout_resistance( 7, 0.039 );
             fanout_resistance( 8, 0.048 );
             fanout_resistance( 9, 0.057 );
             fanout_resistance( 10, 0.06 );
            
            fanout_area(  1, 0.11 );
            fanout_area( 20, 2.20 );